1. Field of the Invention
The present invention relates to a structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET), and more particularly, fabricating a field effect transistor with a triple gate conductive structure formed on a plurality of the underlying FET device channel's trapezoid pillars for drastically increasing the channel conductance area (or width) and the device drive current of this Trapezoid-Triple-Gate FET due to its drastically increased channel conduction width.
2. Description of the Prior Art
Triple-Gate Field Effect Transistors (FET) with increasingly higher device channel conductance, process and device reliabilities, device density and lower production cost are being developed ceaseless. The gate vertical sidewall field effect transistor, as reported at the internet page: http://www.intel.com/pressroom/archive/releases/20020919tech.htm, has been demonstrated by the Intel® researchers.
Intel® researchers have developed a field effect transistor with a three-dimensional triple gate that achieves higher device operation performance with greater power efficiency than the traditional planar (flat) transistors. The Triple-Gate FET of Intel® employs a novel 3-D structure, like a raised, flat plateau with two parallel vertical device conduction sidewalls, which sends the electrical carriers along the top and both parallel vertical sidewalls of the transistor device. This will effectively triple the area available for the electrical carriers to travel, like turning a one-lane road into a three-lane highway, but without taking up more space. The Triple-Gate FET possess relatively higher device channel conductance area (or width) and relatively higher device drive current as well, which makes possible greater ultra-high device density and lower production cost in the future.
Even if Intel® Corp. proved the triple gate transistors that have the higher device channel conductance, more ultra-high device density and lower production cost than flat transistors, the transistors being developed by Intel® Corp. are easier to fall-down or strip-off while requesting relatively lower device size or higher device density. Hence, the disclosed present invention is designed to prevent the triple gate transistors from falling-down or stripping-off.